1. Field of the Invention
The present invention relates to a system and method for translating virtual addresses, that result from effective addresses output by a digital processor, to real addresses in computer memory and, more particularly, to a guess mechanism that speeds up the translation process.
2. Prior Art
The use of Lookaside Tables for converting and translating virtual addresses to real addresses during data processing is well known wherein table entries store previously translated addresses so that they are readily obtainable when the same virtual address is again requested. This technique, which takes advantage of the probability that an address request once processed will be repeated, shortens the time needed for address processing by obviating the need to go to main memory each time the request occurs.
One example of a prior art system using a partitioned Translation Lookaside Buffer (TLB) is found in U.S. Pat. No. 4,367,297 to J. A. Anderson et al, wherein, upon a suitable match with an incoming address, an address stored in the TBL is used for translation, aborting the more time-consuming, conventional multiple-fetch address translation process. Another example of a prior system, this one featuring the use of a pre-translate Table in lieu of a partitioned TBL to speed the translation process, is disclosed in U.S. Pat. No. 4,170,039 to T. J. Beacom et al. It will be seen from these examples and a study of the related art that speedup of the translation process is an inherent problem in the art which has been dealt with in many different ways.
It is an object of the present invention to offer a solution to that problem in a simple, efficient, and improved manner by using a guess mechanism involving an algorithm providing a most-recently-used indication that achieves a high probability of correct guesses.